An important phase in the manufacture and production of IC devices is product testing to assure that each device meets required specifications. Such testing is performed at a test station or test system simply referred to as a "tester". In the case of digital logic IC devices, the tester performs a variety of tests including DC parameter tests, AC parameter tests and AC function or dynamic function tests.
In DC parameter testing, a constant voltage is "forced" at a pin of the DUT and the resulting current at the same or other pins is sensed and measured. Similarly a constant current is forced at a pin of the DUT and the resulting voltage is sensed and measured at the same or other pins. Such stimulating test signals are referred to herein as DC test signals and the responses are referred to as pin signals or DC pin signals. The designation "DC" is used because the DC test signal generator applies constant or steady state voltages or currents at a pin of the DUT for sensing and measuring the steady state characteristics of the DUT.
In AC parameter testing, AC test signals are applied at an input pin of the DUT in the form of data test signals of logic high and low potential levels. Generally the propagation times of the AC test signals through the device and the transition times between logic levels at an output pin of the DUT are sensed and measured. Typically the AC parameter testing measures the propagation times and transition times between logic high potential level signals H, logic low potential level signals L, and high impedance cut off states Z at respective pins of the DUT. The designation "AC" is used because the AC test signal generator generates and switches between data test signals of high and low potential levels and drives the alternating test signals at a pin of the DUT. It is the switching characteristics of the DUT that are sensed and measured at the respective pins.
The function testing of the DUT, also referred to as the AC function testing or dynamic function testing also uses AC test signals but in defined patterns and series at the respective pins of the DUT defined by "truth table" function tests. The testing circuits measure the logic response at the respective output pins of the device and the capability of the DUT to perform its intended logic functions in accordance with the device truth tables. The designation "AC" is used because the AC function testing utilizes the AC test signals of logic high and low potential levels. AC function testing is also used to validate the required voltage levels and timing of the responding AC pin signals. The signals sensed and measured at respective pins of the DUT in response to AC test signals for either AC parameter testing or AC function testing are referred to herein as pin signals or AC pin signals.
The major components of a tester include a CPU controller such as a microprocessor, a power supply which includes a number of power supply units, and a test head which houses the testing circuits and on which the DUT is mounted. A human operator or automated program selects, directs, controls and monitors the DC parameter testing, AC parameter testing and AC function testing at a CRT display and keyboard of the CPU controller. Some testers are more fully automated than others.
The CPU controller includes a function memory which may be a combination of RAM and disk memory for storing AC test data such as AC function operands or vectors and AC test control signals which direct the AC parameter tests and AC dynamic function tests on a DUT mounted on the test head. The microprocessor runs test programs which transfer selected AC function vector data and AC control signal data to the test head for performing particular tests.
The test head contains the test circuits that actually perform the selected tests on a DUT. Each pin of the DUT is separately controlled by separate test circuits formed on a separate pin electronics card (PEC). There is generally one PEC for each pin or group of pins of the IC device being tested. The PEC's are typically vertically mounted in a radial distribution on a so called motherboard. The motherboard includes an interface board and buses for receiving selected function test data and test control signals from the microprocessor controller and distributing them to the respective PEC's. The device being tested is plugged into a load board which is in turn mounted on the PEC's. In high speed production, automated handlers perform this function and "index" the DUT in automatically activated sockets known as contactors. Connectors on each PEC provide continuity of test signal electrical paths from the test circuits on the PEC's through the connectors to the DUT board and to the pins of the DUT.
Other typical components of the test head may include a function sequencer which retrieves and sequences the AC function test data for a function test and delivers the function test data to the PEC memory on a pin electronics card. A timing generator generates programmable clock pulse signals and a reference generator provides the accurate reference voltages for AC parameter and function testing.
The testers relevant to the present invention are known as "distributed resource" testers in contrast to so called "shared resource" testers. Each PEC contains the test circuits for a single pin or group of pins of a DUT mounted on the load board. Each PEC includes the DC test circuits and DC parameter testing components for forcing DC test signal steady state voltages and currents and for sensing and measuring resulting pin signal currents and voltages. The high speed logic circuits for AC parameter tests and AC function tests are also located on each PEC along with the AC comparators. A termination circuit is provided on the PEC for receiving AC pin signals from a DUT pin during AC parameter and AC function tests. This consolidation of test circuits on the PEC is intended to reduce the electrical conductor paths for test signals from the test circuits to the DUT pins and similarly reduce the path for resulting pin signals from the DUT pins to the sensing and measuring comparators to minimize degradation of signals.
In the testers of interest to the present invention, an AC test signal generator or driver circuit is provided on each PEC for sending or driving logic high and low potential level data test signals to a DUT pin. An AC pin signal measurement circuit including a comparator senses the logic high and low potential level AC pin signals received from a DUT pin and determines whether the timing and voltage levels of the signals are correct. The programmable termination circuit on the PEC provides for example a 50 ohm ECL termination for receiving the pin signals.
For AC function tests the PEC includes a function operand or function vector RAM memory for storing the selected truth table function test data. The AC test signal pin driver circuit which is also referred to as the AC function driver circuit converts the function test data to proper logic high and low potential level data test signals to apply at the DUT input pins. The AC test signal driver applies the correct function test pattern to the DUT pin. The AC comparators on the PEC sense the pin signals returning from the DUT output pins and determine the validity of the sensed signals. A separate AC measurement board may be provided to supplement the AC comparator for measuring the time between wave form edges of AC test signals and pin signals during AC parameter testing.
For DC parameter testing, the PEC includes a D/A convertor which receives an appropriate test control digital signal and converts it to a voltage or current. This is used by the DC test signal generator or driver circuit to generate and force a steady state test signal voltage or test signal current.
In a typical distributed resource tester, both the DC test signal circuits and the AC test signal circuits are coupled to the same test signal path from the pin electronics card through the PEC/DUT board connector, and the DUT board, to a pin of a device being tested. During DC parameter testing, the AC test signal circuitry must be disconnected from the test signal electrical path while conversely during AC parameter and function testing the DC test signal circuitry must be disconnected from the test signal electrical path. To accomplish the connecting and disconnecting functions, electromechanical relays are typically used.
Such a microprocessor controlled digital IC tester is described for example in the MCT 2000 R SERIES TEST SYSTEMS HARDWARE MANUAL, Publication Number 010193B, Revision B, Nov. 1, 1986, C 1986 MCT, by Micro Component Technology Inc., 3850 North Victoria Street, P.O. Box 64013, St. Paul, Minn. 55164. This Manual contains the following notice by MCT: "The information contained herein is proprietary and is not to be released or reproduced without the written permission of an officer of Micro Component Technology, Inc." Particular reference is directed to "Chapter 1: System Description".
A disadvantage of conventional testers is that the test signal electrical path from the PEC to the pin of a DUT is a poorly controlled impedance path which corrupts the wave form of driving AC test signals and responding AC pin signals. The relays in particular introduce a discontinuity of path impedance which unacceptably corrupts wave forms in the testing of high speed ECL IC devices.
Furthermore the conventional testers typically provide only a single test signal electrical path from the PEC to the DUT. Such testers are generally adequate only for testing single ended output ECL devices where the DUT constitutes an effective transmission line series termination at the end of the test signal electrical path. In order to test bus type ECL IC devices, a transmission line parallel termination must be provided at the DUT end of the test signal electrical path. This is typically accomplished by adding the required bus termination circuitry on the DUT board or load board at the DUT end of the test signal electrical path. Relays are required to remove the bus termination circuitry during DC parameter testing, introducing further impedance discontinuities in the test signal electrical path.
Some testers have implemented dual test signal electrical paths to a single pin of a DUT for testing bus type DUT's with a transmission line (TL) parallel terminated end. Such testers however still do not provide complementary AC test signals and complementary test signal electrical paths on the PEC's for testing complementary output or differential output type ECL devices. Differential output ECL devices are tested in conventional testers generally by using two separate pin electronics cards operating in opposite complementary phases and generally sequentially. Timing skews between the cards limit the resolution of this conventional method particularly with respect to newer high speed ECL devices.